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A 0.13-/spl mu/m SOI CMOS technology for low-power digital and RF applications

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11 Author(s)
Zamdmer, N. ; Semicond. R&D Center, IBM Corp., Hopewell Junction, NY, USA ; Ray, A. ; Plouchart, J.-O. ; Wagner, L.
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Battery-operated electronic devices that can communicate wirelessly are becoming more and more pervasive. This trend is enabled by technologies that allow low-power digital and RF processing. We present here a 0.13 /spl mu/m, partially-depleted SOI CMOS technology with optimized power-saving and RF properties. Power-saving features include low-V/sub t/, thin-gate-oxide FETs for minimum power dissipation and high performance at low voltage (25 ps inverter delay at 0.7 V V/sub dd/); high-V/sub t/, thick-gate-oxide FETs for low-standby-power SRAM and logic-block power switches; and eight levels of Cu interconnects with low-k ILD (Smeys et al., 2000). RF features include high peak NFET performance (141 GHz f/sub T/ and 98 GHz f/sub max/ at V/sub ds/=1.2 V) and the following group of high-Q passives: inductor (peak simulated differential Q of 50 at 4 GHz, L=0.65 nH), MOS varactor, MIMCAP, and resistors.

Published in:

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

12-14 June 2001