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The gate tunneling current for gate oxide thickness around 2.0 nm or below has been known to increase device leakage and power dissipation, and deteriorate device performance and circuit stability in bulk CMOS. Recently, direct tunneling current models for bulk CMOS circuit simulations have been developed (Choi et al., 1999; Lee and Hu, 2000). The gate-to-substrate tunneling current resulting from the electron tunneling from the valence band (EVB) is significantly less than the tunneling current from the channel into the gate, and its effect can usually be neglected in bulk CMOS devices and circuits. For floating-body partially-depleted (PD) SOI devices, however, the gate-to-body tunneling current charges/discharges the floating-body, thus changing the body voltage and V/sub T/ and affecting circuit operation (Fung et al., 2000). In this paper, we present a detailed study of the effect of gate tunneling current on a high performance 34 Kb L1 directory SRAM in a 1.5 V, 0.18 /spl mu/m PD/SOI technology with L/sub eff/=0.08 /spl mu/m and t/sub ox/=2.3 /spl mu/m. This SRAM was originally designed in a 1.5 V, 0.18 /spl mu/m bulk CMOS technology and has achieved 2.0 GHz cycle time and 430 ps access time (Joshi et al., 2000). It utilizes pseudo-static circuits for robust timing and to facilitate migration to PD/SOI technology.