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High performance sub-50 nm CMOS with advanced gate stack

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4 Author(s)
Qi Xiang ; Technol. Res. Group, Adv. Micro Devices Inc., Sunnyvale, CA, USA ; Bin Yu ; Haihong Wang ; Ming-Ren Lin

CMOS devices down to 40 nm L/sub gate/ were fabricated with an advanced gate stack consisting of ultra-thin nitride/oxynitride (N/O) stack gate dielectrics, pre-doped dual poly-Si gates, and NiSi. The gate stack employed gate dielectric down to 9 /spl Aring/ equivalent oxide thickness (EOT) and achieved very low gate R/sub s/ below 3 /spl Omega//sq. NiSi not only improves gate R/sub s/ and S/D R/sub sd/, but reduces inversion T/sub ox/ by minimizing dopant deactivation during silicidation. Consequently, about 8% I/sub dsat/ improvement for both N- and P-MOS are observed with NiSi. The CMOS devices with the advanced gate stack also showed very high performance. At V/sub dd/ of 0.9 V, drive currents of 657 /spl mu/A/um for NMOS and 290 /spl mu/A/um for PMOS are obtained at off-state leakage of 100 nA/um. These device data are among the best reported to date. Reliability evaluation shows more than 20 years lifetime for the ultra-thin N/O stack films at operating voltage of 0.9 V.

Published in:

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

12-14 June 2001