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Asymmetric source/drain extension transistor structure for high performance sub-50 nm gate length CMOS devices

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7 Author(s)
Ghani, T. ; Portland Technol. Dev., OR, USA ; Mistry, K. ; Packan, P. ; Armstrong, M.
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In this paper, we present for the first time an asymmetric source/drain extension (SDE) transistor structure which can achieve high I/sub DSAT/ at gate dimensions below 50 nm. We demonstrate that this structure alleviates the severe I/sub DSAT/ degradation reported in the literature for devices when gate to source/drain overlap dimensions are reduced to under 20 nm/side (Thomson et al, 1998). Sub-15 nm gate to source/drain overlap is mandatory for supporting gate dimensions below 50 nm (Ghani et al, 2000). Moreover, fabrication of this structure employs a standard process flow in which SDE regions are formed by ion implantation and a subsequent drive-in anneal. Fundamental principles of device operation of the asymmetric SDE transistor are presented followed by a description of the process flow and an in-depth analysis of electrical characteristics and associated trade-offs.

Published in:

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

12-14 June 2001

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