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A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs

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23 Author(s)
Miyashita, K. ; Syst. LSI Div., Toshiba Corp., Yokohama, Japan ; Nakayama, T. ; Oishi, A. ; Hasumi, R.
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This paper demonstrates a 100 nm generation SOC technology (CMOS IV) for the first time. Three types of core devices are presented with optimized gate oxynitrides for their stand-by power conditions. This advanced logic process is compatible with 0.18 /spl mu/m/sup 2/ trench capacitor DRAM and 1.25 /spl mu/m/sup 2/ 6 transistor SRAM. Two kinds of high V/sub dd/ devices can be prepared by the triple gate oxide process. Moreover, for mixed signal applications, Ta/sub 2/O/sub 5/ MIM capacitors are introduced into Cu and low-k interconnects.

Published in:

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

12-14 June 2001