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High-speed bit-parallel systolic multipliers for a class of GF(2 m)

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3 Author(s)
Chiou-Yng Lee ; Dept. of Electr. Eng., Chung Gung Univ., Taiwan, China ; Erl-Huei Lu ; Jau-Yien

Two special operations, called the cyclic shifting and the inner product are defined based on the properties of irreducible all one polynomials. With the two operations, an effective algorithm for computing multiplication over a class of GF(2m) was developed in this paper. The low-complexity bit-parallel systolic multipliers are presented. The multiplier is composed of (m+1)2 identical cells, each of which consisting of one 2-bit AND gate, one 2-bit XOR gate and three 1-bit latches. The multiplier has very low latency and propagation delay, which makes them very fast. Moreover the architectures of the multiplier can also be applied to compute multiplication over the class of GF(2m) in which the elements are represented with the root of an irreducible equally spaced polynomial degree

Published in:

VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on

Date of Conference:

2001