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Maximizing functional test coverage in ASICs using evolutionary algorithms

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4 Author(s)
Aktan, B. ; Enterprise Chipset Div., Intel Corp., Hillsboro, OR, USA ; Shor, M. ; Greenwood, G. ; Doyle, P.

This paper describes a prototype test bench used at the Intel Corporation's Oregon Design Center to functionally test ASICs. The test bench uses an evolutionary algorithm, but a direct approach is not used-i.e., the evolutionary algorithm does not explicity evolve the test patterns. Instead, an indirect approach is used where the evolutionary algorithm evolves a set of control parameters, and it is these parameters that the test bench uses to create the test pattern set. Preliminary test results from a moderate size ASIC are presented to show the effectiveness of our method

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Evolutionary Computation, 2001. Proceedings of the 2001 Congress on  (Volume:1 )

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