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A 6.25 ns random access 0.25 /spl mu/m embedded DRAM

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10 Author(s)
DeMone, P. ; MOSAID Technol. Inc., Kanata, Ont., Canada ; Dunn, M. ; Haerle, D. ; Jin-Ki Kim
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A new embedded DRAM architecture with uniform low latency operation was developed for computing, signal processing, and networking applications. Two hard macro blocks 104 K/spl times/24b and 104 K/spl times/16b, were implemented in a 0.25 micron stacked capacitor blended logic DRAM process. The combination of novel control architecture, circuit design, and physical implementation permitted a simulated worst case row access cycle time of 6.25 ns.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001

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