Skip to Main Content
A 64-bit 80-MHz multimedia DSP core has been designed using 0.15-/spl mu/m CMOS technology. An improved Auto-Backgate-Controlled MT-CMOS (ABC-MT-CMOS) circuit with a charge pump is adopted to suppress the standby leakage current. The dynamic active current of the whole chip was simulated to optimize the size of the switch for the power supply control. The DSP core chip, which integrated 300 kgate logic, 64-kbyte SRAM and charge pump circuit, has only 0.9-/spl mu/A standby leakage current.