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A low-swing clock double-edge triggered flip-flop

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2 Author(s)
Chulwoo Kim ; Dept. of Electr. & Comput. Eng., Illinois Univ., Champaign, IL, USA ; Sung-Mo Kang

A low-swing clock double-edge triggered flip-flop (LSDBF) is developed to reduce power consumption significantly compared to conventional FFs. LSDFF avoids unnecessary internal node transition and reduces conflicting currents. The overall power saving in flip-flop operation is estimated to be 30.2 to 50.8% with additional 78% power savings in a clock network.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001