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A 2/sup nd/ order low-pass log-domain filter is fabricated in a 0.25 /spl mu/m CMOS technology using enhanced lateral bipolar transistors. pMOS devices operating in accumulation are used for the integration capacitors. The filter when tuned to a bandwidth of 22 kHz, consumes 4.1 /spl mu/W from a 1.5 V supply and has an r.m.s. output noise of 0.25 nA. The filter's SNR at 1% THD is 56.1 dB and its maximum S/(N+THD) is 44.9 dB. The chip occupies 0.085 mm/sup 2/.