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To achieve high yield products without degrading the performance, it is important to optimize the device condition, considering the process variation. We present a model parameter extraction methodology to extract the process variation from the E-T (Electrical Test) data. We have estimated the parametric yield of a 0.20 /spl mu/m process SRAM test chip using Monte Carlo simulation and have obtained good agreement compared to measurement. We also performed device optimization using a critical path to improve the parametric yield.