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Parametric yield enhancement system via circuit level device optimization using statistical circuit simulation

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4 Author(s)
M. Miyama ; Semicond. & Integrated Circuits Div., Hitachi Ltd., Tokyo, Japan ; S. Kamohara ; K. Okuyama ; Y. Oji

To achieve high yield products without degrading the performance, it is important to optimize the device condition, considering the process variation. We present a model parameter extraction methodology to extract the process variation from the E-T (Electrical Test) data. We have estimated the parametric yield of a 0.20 /spl mu/m process SRAM test chip using Monte Carlo simulation and have obtained good agreement compared to measurement. We also performed device optimization using a critical path to improve the parametric yield.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001