By Topic

Effects of power-supply parasitic components on substrate noise generation in large-scale digital circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Nagata, M. ; Fac. of Eng., Hiroshima Univ., Japan ; Ohmoto, T. ; Hlurasaka, Y. ; Morie, T.
more authors

Activity controllable noise source and arrayed substrate voltage detectors use a 0.25-/spl mu/m, 2.5-V CMOS technology and enable substrate noise measurements with controlled logic density/activity distributions. These circuits are used for exploring effects of power-supply parasitic components on substrate noise generation in practical large-scale CMOS digital circuits. Spatially distributed parasitic impedances on power-supply and return wirings cause the noise generation locally, and moreover, screen the effect of noise attenuation by parasitic capacitances of logic elements working as charge reservoirs.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001