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A 4 Gb/s serial link tracking clock and data recovery (CDR) circuit fabricated in 0.24 /spl mu/m CMOS technology dissipates 84 mW and occupies 0.3 mm/sup 2/. The input signal is 2/spl times/oversampled by 8 offset-cancelled receive amplifiers per receive clock cycle. The samples are processed by a phase controller to position the receive clocks at the center and the edge of the data eye using a semi-digital dual delay-locked loop (DLL). The quiet-supply p-p jitter of the receive clock is 39 ps with 0.33 ps/mV supply sensitivity. It allows for plesiochronous clocking with a frequency tolerance of /spl plusmn/400 ppm. The worst case phase resolution is <20 ps.
Date of Conference: 14-16 June 2001