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A system LSI memory redundancy technique using an ie-Flash (inverse-gate-electrode flash) programming circuit

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5 Author(s)
M. Yamaoka ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; K. Yanagisawa ; S. Shukuri ; K. Norisue
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A new memory redundancy technique using ie-flash (inverse-gate-electrode flash) memory cells was developed. Ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary to use it in system LSIs, and it can be programmed by logic tester. This new redundancy technique was successfully implemented in the cache memories of a 32-bit RISC microprocessor.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001