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An area-efficient 2 GB/s 256 Mb packet-based DRAM with daisy-chained redundancy scheme

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7 Author(s)
Moon, B.-S. ; Memory Div., Samsung Electron., Kyungki, South Korea ; Chai, J.-W. ; Kim, J.-S. ; Yim, S.-M.
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An area-efficient packet-based 256 Mb DRAM with a 4 bank architecture and a peak bandwidth of 1.0 Gbps/pin at V/sub cc/=2.35 V, Temp=100/spl deg/C is developed. This chip features a daisy chained redundancy scheme, an area-efficient logic block placement and routing technique and a process insensitive DLL with duty error reduction scheme to overcome large chip size penalty and to improve chip yield.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001