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A 0.13 /spl mu/m 6 GHz 256/spl times/32b leakage-tolerant register file

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6 Author(s)
Krishnamurthy, R. ; Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA ; Alvandpour, A. ; Balamurugan, G. ; Shanbhagh, N.
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This paper describes a 256/spl times/32b 4-read, 4-write ported register file for 6 GHz operation in 1.2 V, 0.13 /spl mu/m technology. The local bitline uses a pseudo-static leakage tolerant scheme to achieve 8% faster read performance and 36% higher DC noise robustness (with 6/spl times/ active leakage reduction) compared to dual-Vt scheme optimized for high-performance.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001

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