A 0.13 /spl mu/m 6 GHz 256/spl times/32b leakage-tolerant register file

This paper describes a 256/spl times/32b 4-read, 4-write ported register file for 6 GHz operation in 1.2 V, 0.13 /spl mu/m technology. The local bitline uses a pseudo-static leakage tolerant scheme to achieve 8% faster read performance and 36% higher DC noise robustness (with 6/spl times/ active leakage reduction) compared to dual-Vt scheme optimized for high-performance.