By Topic

An approach to mapping the timing behavior of VLSI circuits on emulators

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sabet, P.B. ; Paris VI Univ., France ; Vuillemin, L.

The time spent in simulation grows in an exponential form with the complexity of the circuit. Therefore, improving the simulation speed can represent a significant profit regarding the verification time. Several approaches can be used to speedup the simulation. These recent years, FPGAs have been used to develop emulators. These systems are composed of several thousands of FPGAs connected together through a programmable network. Although this approach seems very attractive with regard to the speedup, all the information included in a circuit description cannot be mapped on the emulator. In this paper, we propose a method to reproduce the timing behavior of the circuit on an emulator

Published in:

Rapid System Prototyping, 12th International Workshop on, 2001.

Date of Conference: