Prototyping of efficient hardware algorithms for data compression in future communication systems

Due to the high bandwidth requirements of up to 2 Mbit/s in 3rd-generation mobile communication systems, efficient data compression approaches are necessary to reduce communication and storage costs. The status of recent VLSI technologies promises complete system-on-a-chip (SoC) solutions for both mobile and network-based communication systems, including new compression algorithms based on the Burrows-Wheeler transform (BWT). The most complex task of the BWT algorithm is its lexicographic sorting of n cyclic rotations of a given string of n characters. This paper discusses the feasibility and VLSI implementation of this scalable BWT architecture in simulating and prototyping its systolic, highly utilized hardware structure with Virtex FPGAs