Modeling CMOS gates driving RC interconnect loads

The problem of estimating the performance of CMOS gates driving RC interconnect loads is addressed in this paper. The widely accepted π-model is used for the representation of an interconnect line that is driven by an inverter. The output waveform and the propagation delay of the inverter are analytically calculated taking into account the coupling capacitance between input and output and the effect of the short-circuit current. In addition, short-circuit power dissipation is accurately estimated. Once the voltage waveform at both the beginning and the end of an interconnect line are obtained, a simple method is employed in order to calculate the voltage waveform at each point of the line