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An efficient systolic architecture for the DLMS adaptive filter and its applications

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2 Author(s)
Lan-Da Van ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Wu-Shiung Feng

In this paper, we propose an efficient systolic architecture for the delay least-mean-square (DLMS) adaptive finite impulse response (FIR) digital filter based on a new tree-systolic processing element (PE) and an optimized tree-level rule. Applying our tree-systolic PE, a higher convergence rate than that of the conventional DLMS structures can be obtained without sacrificing the properties of the systolic-array architecture. The efficient systolic adaptive FIR digital filter not only operates at the highest throughput in the word-level but also considers finite driving/update of the feedback error signal. Furthermore, based on our proposed optimized tree-level rule that takes account of minimum delay and high regularity, an efficient N-tap systolic adaptive FIR digital filter can be easily determined under the constraint of maximum driving of the feedback error signal

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:48 ,  Issue: 4 )