By Topic

Implementation of DSP-RAM: an architecture for parallel digital signal processing in memory

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
B. S. -H. Kwan ; Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada ; B. F. Cockburn ; D. G. Elliott

We describe a synthesizable implementation in VHDL of a parallel architecture for signal processing called DSP-RAM. DSP-RAM is an enhanced version of the earlier computational RAM (C-RAM) architecture proposed by Elliott (see Ph.D. thesis, Dept.of Electrical Engineering, University of Toronto, Canada, 1998). Like C-RAM, the new architecture integrates on the same chip both memory storage and single instruction stream, multiple data stream parallel data processing. Unlike in C-RAM, each processing element contains a multiplier-accumulator that can directly handle 16-bit data words; in contrast, C-RAM is organized to perform massively-parallel, bit-serial computation. The VHDL DSP-RAM model was verified by simulating three promising applications: FIR digital filtering, the discrete cosine transform (DCT), and vector quantization (VQ). A controller circuit along with a simple micro-programming language were also designed to facilitate the implementation of applications

Published in:

Electrical and Computer Engineering, 2001. Canadian Conference on  (Volume:1 )

Date of Conference: