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VLSI design and implementation of WCDMA channel decoder

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5 Author(s)
Xu Youyun ; Electron. Eng. Dept., Shanghai Jiaotong Univ., China ; Li Zongwang ; Ruan Ming ; Luo Hanwen
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We present a memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder module (including a de-interleaving and de-multiplexing processing unit, a turbo decoder, a Viterbi decoder, etc.) on a single Xilinx XVC1000E FPGA chip. Using a modified MAP algorithm, say parallel sliding window logarithmic maximum a posteriori (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8i chip-clock (30.72 MHz) driving can concurrently process a data rate up to 2.5~5 Mbps of turbo coded sequences and a data rate over 400 kbps of convolutional codes under a reasonable BER performance. If the de-interleaving and de-multiplexing processing unit is excluded, there is no external memory needed. Test results show that the decoding performance of these two type channel decoders is only 0.2-0.25 dB or less loss compared to float simulations

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Electrical and Computer Engineering, 2001. Canadian Conference on  (Volume:1 )

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