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A genetic algorithm for testable data path synthesis

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3 Author(s)
Harmanani, H. ; Dept. of Comput. Sci., Lebanese Univ., Beirut, Lebanon ; Saliba, R. ; Khoury, M.

A high level synthesis for testability method is presented with the objective to generate testable resistor transistor logic designs from behavioral descriptions. The approach is formulated as an allocation problem and solved using an efficient genetic algorithm that generates cost-effective testable designs. We follow the allocation method with an automatic test point selection algorithm that trades off design area and delay with test quality. The method is implemented and design comparisons are reported

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Electrical and Computer Engineering, 2001. Canadian Conference on  (Volume:1 )

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