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CMOS image sensor camera with focal plane edge detection

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2 Author(s)
Tabet, Muahel ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Hornsey, R.

We present a simple, yet robust, VLSI implementation of sampled-method edge detection. Our technique adopts the well-known correlated double sampling (CDS), usually used for fixed pattern noise (FPN) reduction, to perform a sampled differentiation of the captured image to detect visual edges. This circuit is usually an integral part of most CMOS image sensors; therefore no additional area is required to include the proposed edge detection functionality in the image sensor. The imager array was implemented using active pixel sensor (APS) technology with dual mode of operation: a logarithmic (continuous) mode with wide optical dynamic range and a linear (integrating) mode with higher image quality. The real-time edge detection was demonstrated in the both modes of operation. This technique can be easily extended to perform temporal differentiation, providing a simple method for motion detection. The prototype chip was fabricated using standard 0.5 μm CMOS process with an array of 64×64 pixels and pixel size of 30×30 μm. The fill factor is ~60% and the system working voltage is 3.3 V. Results indicate that the proposed architecture is suitable for applications such as security, and industrial inspection, where integrated functionalities are advantageous

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Electrical and Computer Engineering, 2001. Canadian Conference on  (Volume:2 )

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