A virtual clock enhancement method for DDS using an analog delay line

In this paper, we describe an analog delay line (DL) used for virtual clock enhancement in a direct digital synthesis (DDS). The novelty of the proposed method is the immediate application of the output signal of the phase accumulator for the generation of the desired frequency. To obtain the necessary spectral purity of the generated frequency, additional digital signal processing (DSP) based on a delay-locked loop (DLL) and noise shaping is applied. The consequences of nonlinear effects within the DL for the spectral performance of the DDS are explained.