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Evolutionary graph generation with terminal-colour constraint for heterogeneous circuit synthesis

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3 Author(s)
Natsui, M. ; Higuchi Lab., Tohoku Univ., Sendai, Japan ; Aoki, T. ; Higuchi, T.

A novel graph-based evolutionary optimisation technique that can be used to synthesise heterogeneous circuits consisting of various different components is proposed. The key idea is to introduce “circuit graphs with coloured terminals” for modelling heterogeneous architectures. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit

Published in:

Electronics Letters  (Volume:37 ,  Issue: 13 )