Cart (Loading....) | Create Account
Close category search window
 

Evolutionary graph generation with terminal-colour constraint for heterogeneous circuit synthesis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Natsui, M. ; Higuchi Lab., Tohoku Univ., Sendai, Japan ; Aoki, T. ; Higuchi, T.

A novel graph-based evolutionary optimisation technique that can be used to synthesise heterogeneous circuits consisting of various different components is proposed. The key idea is to introduce “circuit graphs with coloured terminals” for modelling heterogeneous architectures. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit

Published in:

Electronics Letters  (Volume:37 ,  Issue: 13 )

Date of Publication:

21 Jun 2001

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.