By Topic

Experiences in developing a research-focused project course: IP-core based IC design enabled by 3D wafer bonding

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jian-Qiang Lu ; Center for Integrated Electron. & Electron. Manuf., Rensselaer Polytech. Inst., Troy, NY, USA ; Gutmann, R.J.

Three-dimensional (3D) integrations offer the potential of reducing fabrication and performance limitations of future generations of planar ICs. Our approach using dielectrics as the bonding glue layer provides a monolithic 3D integration process, which is fully compatible with back-end-of-the-line processing. This 3D technology enables heterogeneous systems, such as future electronic and photonic systems using a mix-and-match hard IP core design approach. We offer a new course on core-based IC design and technology, with both 2D and 3D implementations.

Published in:

Microelectronic Systems Education, 2001. Proceedings. 2001 International Conference on

Date of Conference:

17-18 June 2001