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Three-dimensional (3D) integrations offer the potential of reducing fabrication and performance limitations of future generations of planar ICs. Our approach using dielectrics as the bonding glue layer provides a monolithic 3D integration process, which is fully compatible with back-end-of-the-line processing. This 3D technology enables heterogeneous systems, such as future electronic and photonic systems using a mix-and-match hard IP core design approach. We offer a new course on core-based IC design and technology, with both 2D and 3D implementations.