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Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling

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2 Author(s)
Wen-Chin Lee ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Chenming Hu

A semi-empirical model is proposed to quantify the tunneling currents through ultrathin gate oxides (1-3.6 nm). As a multiplier to a simple analytical model, a correction function is introduced to achieve universal applicability to all different combinations of bias polarities (inversion and accumulation), gate materials (N+, P+ , Si, SiGe) and tunneling processes. Each coefficient of the correction function is given a physical meaning and determined by empirical fitting. This new model can accurately predict all the current components that can be observed: electron tunneling from the conduction band (ECB), electron tunneling from the valence band (EVB), and hole tunneling from the valence hand (HVB) in dual-gate poly-Si1-xGex-gated (x=0 or 0.25) CMOS devices for various gate oxide thicknesses. In addition, this model ran also be employed to determine the physical oxide thickness from I-V data with high sensitivity. It is particularly sensitive in the very-thin-oxide regime, where C-V extraction happens to be difficult or impossible (because of the presence of the large tunneling current)

Published in:

Electron Devices, IEEE Transactions on  (Volume:48 ,  Issue: 7 )

Date of Publication:

Jul 2001

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