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A full Cu damascene metallization process for sub-0.18 /spl mu/m RF CMOS SoC high Q inductor and MIM capacitor application at 2.4 GHz and 5.3 GHz

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7 Author(s)
C. C. Lin ; Res. Dev. Center, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan ; H. M. Hsu ; Y. H. Chen ; T. Shih
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A full Cu damascene metallization process was successfully developed for simultaneous formation of sub-0.18 μm RF CMOS passive components including circular spiral inductor and MIM capacitor. High quality factor inductor with Q=18 at 1.2 nH was achieved by applying highly uniform Cu CMP process on polishing microns of Cu. Less than 2% Rs uniformity and 70 nm dishing on 95% density Cu line were achieved on 8" wafers for finished 2.5 μm thick Cu inductor. Q factor has been doubled from 6 to 13 at 2.4 GHz when alternating the 3.5 turns inductor material from Al to Cu. The low sheet resistance on the inductor top plate allows for good Q value. Pre-CMP anneal condition was found crucial for final Cu surface morphology which in terms affecting the breakdown characteristic of the MIM capacitor. In this work, it was found that stressing the Cu with pre-CMP high temperature anneal can relieve the Cu surface hillock formation after the MIM insulator deposition. As a result, with the pre-CMP high temperature anneal, the breakdown voltage can be improved to 4 times better than the one with no or low temperature pre-CMP anneal. The breakdown field improvement is calculated to be up to 6.6 M V/cm. This power MOS can be used for both Bluetooth (around 2.4 GHz) and wireless LAN (around 5.3 GHz) applications by inductor layout optimization on peak-Q value at specified frequency.

Published in:

Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International

Date of Conference:

6-6 June 2001