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A new analytical thermal model for multilevel ULSI interconnects incorporating via effect

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3 Author(s)
Ting-Yen Chiang ; Center for Integrated Syst., Stanford Univ., CA, USA ; K. Banerjee ; K. C. Saraswat

This paper presents a compact analytical model for estimating the temperature rise of multilevel ULSI interconnects incorporating the via effect. For the first time, an analytical expression is derived for the via correction factor, η, which quantifies the effect of via separation on the effective thermal conductivity of ILD (inter-layer dielectrics), k ILD,effective, with k ILD,effective=k ILD/k ILD,effective, where 0<η<1. Both the temperature profile along the metal lines and average temperature rise of the lines can be easily obtained using this analytical model. The predicted temperature profiles are shown to be in excellent agreement with the 3-D finite element thermal simulation results. The model is then applied to estimate the temperature distribution in multi-level interconnects. Significant difference in temperature distribution and maximum temperature rise is observed between the realistic situation of heat dissipation with vias and the overly simplified case that ignores via effect.

Published in:

Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International

Date of Conference:

6-6 June 2001