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A design environment for high throughput, low power dedicated signal processing systems

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8 Author(s)
Davis, W.R. ; California Univ., Berkeley, CA, USA ; Ning Zhang ; Camera, K. ; Chen, F.
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A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. A modular framework based on a combined Simulink and floorplan description drives automatic layout generation. Automatic characterization of layout improves system-level estimates. The flow is demonstrated on the subsystems of CDMA and OFDM receivers and a 300 k transistor test-chip

Published in:

Custom Integrated Circuits, 2001, IEEE Conference on.

Date of Conference:

2001