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Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS

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11 Author(s)
Miyake, T. ; Device Dev. Center, Hitachi Ltd., Tokyo, Japan ; Yamashita, T. ; Asari, N. ; Sekisaka, H.
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A new design methodology of high performance CMOS MPU that applies ultra-low VTH, which is necessary to improve circuit performance with low power supply voltage, is discussed. The multi-VTH, the IDDQ measurement with back bias control at low temperature and IDDQ technologies are applied in order to speed up, without increasing background leakage, IDDQ test. As a result, operation frequency of 64 bit MPU was successfully improved 340 MHz to 560 MHz without lowering IDDQ quality

Published in:

Custom Integrated Circuits, 2001, IEEE Conference on.

Date of Conference:

2001

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