By Topic

A ROM-less direct digital frequency synthesizer using segmented nonlinear digital-to-analog converter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jiandong Jiang ; Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA ; E. K. F. Lee

A direct digital frequency synthesizer (DDFS) based on nonlinear digital-to-analog converter (DAC) is presented. A new technique is proposed to segment the nonlinear DAC such that high speed DDFS with low power consumption and small die area can be achieved. The DDFS has 12 bits of phase resolution and 11 bits of magnitude resolution. It was fabricated in a 0.25 μm CMOS process with an active area of 1.4 mm 2. For a clock frequency of 300 MHz, the spurious free dynamic range (SFDR) is better than 50 dB with output frequencies up to 3/8 of the clock frequency

Published in:

Custom Integrated Circuits, 2001, IEEE Conference on.

Date of Conference: