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A 900 MS/s 6b interleaved CMOS flash ADC

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2 Author(s)
Baiying Yu ; Analog & Mixed-Signal Design Center, Iowa State Univ., Ames, IA, USA ; Black, W.C., Jr.

A 900 MS/s, 6 bit, 4-way, time-interleaved flash ADC is demonstrated. The 4 on-chip ADCs share a common reference string and preamplifiers to minimize the mismatch between channels. The measured SNDR is over 31 dB at 900 MHz with analog input at 1.1 MHz. The chip has been fabricated in a standard 0.25 μm CMOS process and occupies an active area of 2.08 mm2

Published in:

Custom Integrated Circuits, 2001, IEEE Conference on.

Date of Conference:

2001