A 'digital' 6-bit ADC in 0.25 /spl mu/m CMOS

Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes usually have an adverse effect on area and power consumption, and more seriously do not scale easily to low voltage processes. We describe a digital technique, which removes the accuracy constraints from the comparators. With no analog matching requirement, the comparators can be small, fast and power efficient. A 6-bit prototype converter built in a standard 0.25 /spl mu/m digital CMOS process occupies 1.2 mm/sup 2/ and dissipates 110 mW from a 2.2 V supply at 300 Ms/s.