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Fast clock-jitter simulation in continuous-time delta-sigma modulators

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2 Author(s)
P. Benabes ; Service des Meas., SUPELEC, Gif-sur-Yvette, France ; R. Kielbasa

A new methodology for clock-jitter simulation in continuous-time sigma-delta (ΣΔ) converters is proposed. This analysis method, based on a previously published method uses a discrete time simulator, which is more efficient than an analog simulator. Only one sample per output sample is required which reduces simulation times to a few seconds, even for large simulations. Results are compared to those obtained with time-domain state-equations integration

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Instrumentation and Measurement Technology Conference, 2001. IMTC 2001. Proceedings of the 18th IEEE  (Volume:3 )

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