By Topic

2-bit adder carry and sum logic circuits clocking at 19 GHz clock frequency in transferred substrate HBT technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Mathew, T. ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Jaganathan, S. ; Scott, D. ; Krishnan, S.
more authors

We report carry and sum circuits for a 2-bit adder. The 2-bit adders are designed to be part of a pipelined 2N-bit adder-accumulator. The ICs clock at a maximum of 19 GHz and were fabricated in InAlAs/InGaAs transferred substrate HBT technology. To obtain high clock rates in a design with multiple gate delays, we have employed a novel merged AND-OR logic structure using 4-level series-gated current-steering logic. Further, this logic is merged with the synchronizing latch circuit so as to minimize the overall gate delay. The 2-bit carry circuit has 250 transistors, a maximum clock frequency of 19 GHz, and dissipates 1.2 W. The sum logic circuit of a full adder was realized as a 4-level series-gated ECL XOR gate. This circuit has a maximum clocking frequency of 24 GHz, has 150 transistors and dissipates 750 mW

Published in:

Indium Phosphide and Related Materials, 2001. IPRM. IEEE International Conference On

Date of Conference: