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FeRAM retention analysis method based on memory cell read signal voltage measurement

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5 Author(s)
H. Koike ; Silicon Syst. Res. Labs., NEC Corp., Sagamihara, Japan ; K. Amanuma ; T. Miwa ; J. Yamada
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A novel retention analysis method for ferroelectric random access memory (FeRAM) has been developed, in which read signal voltages from memory cells are measured. It employs on-chip sample/hold circuits, an off-chip A/D converter, and memory LSI testing equipment. FeRAM chip reliability is estimated on the basis of FeRAM read signal voltages after retention periods of 1 day and longer. When used as a tool to estimate long-term data retention in FeRAM chips, and when used to analyze fluctuations in FeRAM cell characteristics, this method can be of significant help in improving the reliability of FeRAM chips

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Microelectronic Test Structures, 2001. ICMTS 2001. Proceedings of the 2001 International Conference on

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