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Token scan cell for low power testing

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2 Author(s)
T. -C. Huang ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; K. -J. Lee

A multiphase clocking technique is presented for reducing the test power for scan-based circuits. A novel scan cell design called the token scan cell is developed, which combines a phase-generating flip-flop and a data flip-flop to overcome the inter-phase skew and clock routing problems. Experimental results show that on average ~87% of the data transition count during scanning is reduced. For many circuits with long chains, a reduction of >98% can even be achieved

Published in:

Electronics Letters  (Volume:37 ,  Issue: 11 )