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Bit-parallel systolic multipliers for GF(2m) fields defined by all-one and equally spaced polynomials

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3 Author(s)
Chiou-Yng Lee ; Dept. of Electr. Eng., Chang Gung Univ., Tao-Yuan, Taiwan ; Erl-Huei Lu ; Lee, Jau-Yien

Two operations, the cyclic shifting and the inner product, are defined by the properties of irreducible all one polynomials. An effective algorithm is proposed for computing multiplications over a class of fields GF(2m) using the two operations. Then, two low-complexity bit-parallel systolic multipliers are presented based on the algorithm. The first multiplier is composed of (m+1)2 identical cells, each consisting of one 2-input AND gate, one 2-input XOR gate, and three 1-bit latches. The other multiplier comprises of (m+1)2 identical cells and mXOR gates. Each cell consists of one 2-input AND gate, one 2-input XOR gate, and four 1-bit latches. Each multiplier exhibits very low latency and propagation delay and is thus very fast. Moreover, the architectures of the two multipliers can be applied in computing multiplications over the class of fields GF(2m ) in which the elements are represented with the root of an irreducible equally spaced polynomial of degree m

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Computers, IEEE Transactions on  (Volume:50 ,  Issue: 5 )