By Topic

The impact of interconnection and dielectric materials on the time delay of scaled memory-adder systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
K. Nikolic ; Dept. of Phys. & Astron., Univ. Coll. London, UK ; D. Berzon ; M. Forshaw

This paper examines how the use of copper instead of aluminum and the use of low dielectric constant material instead of standard oxide materials for chip wiring would improve the signal delay in a typical microprocessor. The minimum feature size (MOSFET gate length) of basic elements, MOSFETs and interconnects, is scaled in the range of 550 nm-50 nm. Our results suggest that, for example, a 50% decrease of the interconnect resistance will bring only a very moderate improvement (up to a few percent), whereas the reduction of dielectric constant by 50% would have a very strong impact of almost 50% reduction in the time delay for the local line structures

Published in:

IEEE Transactions on Electron Devices  (Volume:48 ,  Issue: 6 )