An implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation

A new parallel semiconductor device simulation using the dynamic load balancing approach is presented. This semiconductor device simulation based on adaptive finite volume error estimation, and monotone iterative methods has been developed and implemented on a Linux-cluster with MPI library. Two different parallel versions of the algorithm to perform a complete device simulation are proposed. The first one is a dynamic parallel domain decomposition approach. The second version is a parallel current-voltage characteristic points simulation. The implementation shows that a well-designed load balancing simulation can reduce the execution time up to an order of magnitude. Compared with the measured data, numerical simulations on P-N diode, N-MOSFET, and DTMOS devices are presented to show the accuracy and efficiency of the method.