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A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system

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4 Author(s)
Yong-Ha Park ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Seon-Ho Han ; Jung-Hwan Lee ; Hoi-Jun Yoo

A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping, memory-coupled logic pipeline, low-power operation, 7.1-GB/s memory bandwidth, and 11.1-Mpolygon/s drawing speed. The 56-mm2 prototype die integrating one edge processor, eight pixel processors, eight frame buffers, and a RISC core are fabricated using 0.35-μm CMOS embedded memory logic (EML) technology with four poly layers and three metal layers. The fabricated test chip, 590 mW at 100 MHz 3.3 V operation, is demonstrated with a host PC through a PCI bridge

Published in:

IEEE Journal of Solid-State Circuits  (Volume:36 ,  Issue: 6 )