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A self-timed divider using a new fast and robust pipeline scheme

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3 Author(s)
Jing-ling Yang ; Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China ; Chiu-Sing Choy ; Cheong-Fat Chan

This paper investigates the potential of self-timed property of differential cascode voltage switch logic (DCVSL) circuits, and examines architectural techniques for achieving self-timing in DCVSL circuits. As a result, a fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. The proposed self-timed datapath scheme is verified by an 8-bit divider which is implemented using AMS 0.6-μm CMOS technology, and the chip size is about 1.66 mm×1.70 mm. The chip testing results show that the divider functions correctly and the latency for 8-bit quotient-digit generation is 17 ns (about 58.8 MHz)

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:36 ,  Issue: 6 )