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Interconnect performance estimation models for design planning

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2 Author(s)
Cong, J. ; Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA ; Zhigang Pan

This paper presents a set of interconnect performance estimation models for design planning with consideration of various effective interconnect layout optimization techniques, including optimal wire sizing, simultaneous driver and wire sizing, and simultaneous buffer insertion/sizing and wire sizing. These models are extremely efficient, yet provide high degree of accuracy. They have been tested on a wide range of parameters and shown to have over 90% accuracy on average compared to running best-available interconnect layout optimization algorithms directly. As a result, these fast yet accurate models can be used efficiently during high-level design space exploration, interconnect-driven design planning/synthesis, and timing-driven placement to ensure design convergence for deep submicrometer designs

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:20 ,  Issue: 6 )

Date of Publication:

Jun 2001

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