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A design framework to efficiently explore energy-delay tradeoffs

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4 Author(s)
W. Fornaciari ; Dipartimento di Elettronica, Politecnico di Milano, Italy ; D. Sciuto ; C. Silvano ; V. Zaccaria

Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance constraints. In this paper, we propose a system-level design methodology for the efficient exploration of the memory architecture from the energy-delay combined perspective. The aim is to find a sub-optimal configuration of the memory hierarchy without performing the exhaustive analysis of the parameters space. The target system architecture includes the processor, separated instruction and data level-one caches, the main memory, and the system buses. The methodology is based on the sensitivity analysis of the optimization function with respect to the tuning parameters of the cache architecture (mainly cache size, block size and associativity). The effectiveness of the proposed methodology has been demonstrated through the design space exploration of a real-world example: a MicroSPARC2-based system running the Mediabench suite. Experimental results have shown an optimization speedup of 329 times with respect to the full search, while the near-optimal system-level configuration is characterized by a distance from the optimal full search configuration in the band of 10%.

Published in:

Hardware/Software Codesign, 2001. CODES 2001. Proceedings of the Ninth International Symposium on

Date of Conference:

25-27 April 2001