Referenced Items are not available for this document.
This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the transistor-level design of multiple-valued arithmetic circuits. An important feature of EGG is its capability to optimize general graph structures directly instead of encoding the structures into indirect representations, such as bit strings and trees. The potential capability of EGG is demonstrated through an experimental synthesis of a radix-4 signed-digit full adder circuit
Published in:
Multiple-Valued Logic, 2001. Proceedings. 31st IEEE International Symposium on
Date of Conference: 2001
- Page(s):
- 253 - 258
- Meeting Date :
- 22 May 2001-24 May 2001
- ISSN :
- 0195-623X
- Print ISBN:
- 0-7695-1083-3
- INSPEC Accession Number:
- 6978260
- Conference Location :
- Warsaw
- Digital Object Identifier :
- 10.1109/ISMVL.2001.924581
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
