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Josephson shift register design and layout

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3 Author(s)
Przybysz, J.X. ; Westinghouse Res. & Dev. Center, Pittsburgh, PA, USA ; Blaugher, R.D. ; Buttyan, J.

Integrated circuit chips were designed and fabricated, based on a Josephson shift register circuit that simulated operation at 25 GHz using the SPICE program. The 6.25-mm2 chip featured a twelve-gate, four-stage shift register fabricated with Nb/AlOx/Nb Josephson junctions with a design value of 2000 A/cm2 critical current density. SUPERCOMPACT, a general program for the design of monolithic microwave integrated circuits, was used to model the effects of layout geometry on the uniformity and phase coherence of logic gate bias currents. A layout geometry for the superconductive transmission lines and thin-film bias resistors was developed. The original SPICE-designed circuit was modified as a result of these calculations. Modeling indicated that bias current variations could be limited to 3% for all possible logic states of the shift register, and phase coherence of the gates could be maintained to within 2° at 10 GHz. The fundamental soundness of the circuit design was demonstrated by the proper operation of fabricated shift registers

Published in:

Magnetics, IEEE Transactions on  (Volume:25 ,  Issue: 2 )